Hi Ron, I removed the dhcp-server installed on my host PC and it had no effect. The same outcome as before. Anything that might be different between your settings and mine? Thanks again.
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Forum Post: RE: Linux/TMDSICE3359: TFTP boot
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Forum Post: RE: AM5728: TMDSEVM572X
Thanks for promoting our Sitara Processor devices. Let me check with our EVM team and more details will be posted here soon.
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Forum Post: RE: TMS320C5515: Is the XDS560v2 compatible with the C5515?
Perhaps the XDS200 would be better than either actually!Thanks for the reference.
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Forum Post: RE: Linux/TMDSICE3359: TFTP boot
Here is a full log; U-Boot 2018.01-g9d984f4548 (Apr 06 2019 - 07:42:30 +0000) CPU : AM335X-GP rev 2.1 Model: TI AM3359 ICE-V2 DRAM: 256 MiB ETH0, CPSW ETH1, CPSW NAND: 0 MiB MMC: OMAP SD/MMC: 0 Net: cpsw, usb_ether Hit any key to stop autoboot: 0 => setenv ethact cpsw => setenv serverip 192.168.2.60 => run findfdt => run init_console => run args_mmc => pr bootcmd bootcmd=if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd => pr bootargs bootargs=console=ttyO3,115200n8 root=PARTUUID=b1396df8-02 rw rootfstype=ext4 rootwait => dhcp link up on port 0, speed 100, full duplex BOOTP broadcast 1 DHCP client bound to address 192.168.2.64 (12 ms) =>
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Forum Post: RE: OMAP-L138: USB times out in Windows 10
Hello David, Unfortunately, we don't have any baremetal USB examples in Processor SDK, and Starterware is in maintenance mode and has not been updated to work with Windows 10. In Processor SDK, the USB examples that we have for OMAPL138 are USB device audio, USB Host Msc, and USB Device Msc, but they are RTOS based.
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Forum Post: RE: Linux/AM5728: PWM on Timer15
Hello, I am wondering if you have enabled timer15 in the dts file. Also, I do not see any "pinctrl-0" definition in your code. Regards, Krunal
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Forum Post: 66AK2H06: how to set exception propely?
Part Number: 66AK2H06 Hi all, how to i set the exception properly with CSL? i try to use the same way with normal interrupt but it doesn't work. here is my code int eventIDNMI[] = // CIC module output to INTC module input { CSL_C66X_COREPAC_TIMER_11_INTL, }; _IntcVectId vectIDNMI[] = { CSL_INTC_VECTID_EXCEP, CSL_INTC_VECTID_7, }; hIntcNMI[0] = CSL_intcOpen(&intcObj, eventIDNMI[0], &vectIDNMI[0], NULL); CSL_intcHookIsr(vectIDNMI[0], NMI_ISR_handler[0]); // Hook the ISR's CSL_intcHwControl(hIntcNMI[0], CSL_INTC_CMD_EVTCLEAR,NULL); // Clear any pending interrupts CSL_intcHwControl(hIntcNMI[0], CSL_INTC_CMD_EVTENABLE,NULL); // Clear any pending interrupts then i set the register TSR to enable it. Uint32 chipReg[1]; chipReg[0] = CSL_chipReadReg (CSL_CHIP_TSR); CSL_chipWriteReg (CSL_CHIP_TSR, chipReg[0] | 0x0000000c); // enable all exception I want to use timer 11 to trigger exception but if it doesn't work. it is ok to use CSL_INTC_VECTID_7 for the normal interrupt but I want the DSP can use CSL_INTC_VECTID_EXCEP for the exception. Does anyone know how to set exception properly? Thanks
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Forum Post: TMDX654IDKEVM: x2 Lane PCIe Card Clocking Root Selection Issue
Part Number: TMDX654IDKEVM Our customer want to select the clock source for PCIe RC and EP operation on IDK. Resistor options are provided to do that. But some pads for the resistor options cannot be found. Where is each pad of R245 and R246 on the PCIe card? Best regards, Daisuke
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Forum Post: AM3358: Overvoltage on 1.8V rail
Part Number: AM3358 Hi, I designed the board using "AM3358BZCZ100", but the product behaves differently at power on. Of the five, there are some that start normally, some that start occasionally, and some that do not start at all. The cause is that the “LDO1 pin(1.8V)” of “ TPS65218D0 ” transiently rises to 2 V when the power is turned on. Due to this overvoltage, the power supply start-up sequence of " TPS65218D0 " stops halfway. In order to investigate the cause, I removed the load of "LDO1" from group 1 to 3 in order. LDO1 connect group (group1) analog circuits load = 100uA VDDA_ADC VREF_P (group2) VDDS VDDS_SRAM_CORE_BG VDDS_SRAM_MPU_BB VDDS_RTC (group3) VDDS_PLL_CORE_LD VDDS_PLL_MPU VDDS_PLL_DDR VDDS_OSC When group 3 was removed, it now works properly. It seems that an overvoltage will be applied from the “AM3358BZCZ100 PLL,OSC” terminal to the “LDO1” when the power is turned on for some reason. By adding a 500 ohm resistor as a load to the “LDO1” terminal, the overvoltage does not appear. Is it the characteristic of "AM3358BZCZ100"? Is there a problem with using "AM3358BZCZ100"? Regards, Isao.
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Forum Post: PROCESSOR-SDK-AM335X: Compilation error
Part Number: PROCESSOR-SDK-AM335X Hi, I created a project for turning on LED according to Processor RTOS Getting Started Guide Section 6.5 GPIO, but it is showing some error. I am attaching a JPEG File. Please suggest any solution. Regards Gaurav
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Forum Post: Unable to get MSI Interupt generated at RP.
I'm a part of post silicon validation. I'm trying to generate an MSI Interrupt at RP, but could not do so. I have EP PCIe card connected to RP. 1. Enabled BME and Memory space at both EP and RP. 2. Enabled MSI at both EP & RP. 3. Current MSI address at EP is 0x0 4. Current MSI Data at EP - 0x0 5. Current MSI address at RP is 0x3fb83c03 6. Current MSI Data at RP is 0x41c I'm not understanding how to configure MSI address (based upon current RP address?) And how to check if actually MSI Interrupt generated or not?
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Forum Post: TDA2EVM5777: TIDL issues with Tensorflow 1.1 networks import
Part Number: TDA2EVM5777 hello everybody , please During conversion of several networks from Tensorflow 1.10 to TIDL format, using the import tool, these issues were found: Op Type Shape is Not suported Op Type StridedSlice Op Type Pack Op Type Conv2DBackpropInput Op Type Maximum could you help ? where can I find details on TIDL limitations ? thank you best regards Carlo
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Forum Post: TDA2EVM5777: how to modify input file for TDA2 evm on SDcard
Part Number: TDA2EVM5777 Hi everybody , please about the input video file to be placed together with the final files on the SD card of the board. The video provided from TI ( inputdata ) , that is also used in the segmatic demo, is in a binary format and it is not possible to convert it to a standard video file. I would like to know how to change the input video , and how to create it froma a standard video format . best regards Carlo
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Forum Post: Linux/TMDSICE3359: Boot time optimization
Part Number: TMDSICE3359 Tool/software: Linux sdk 5.01 Linux RT arago. AM3359 Industrial Communications Engine (ICE) Hi! I have to minimize the time of boot of ICE. So, I have remove the sevices, by "systemctl disable [service]" and by remove the links from rcX.d. Result: the boot time has no changed. Am I have to setup the uboot? By changing the dts-files?
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Forum Post: RTOS/AM5728: I2C R/W inconsistency
Part Number: AM5728 Tool/software: TI-RTOS Hi, this is the follow up question to the problem mentioned in the link below we were able to address the problem by doing the code download from the ARM(linux) because it was very consistently taking around 4 sec for doing the same download but the DSP still has to communicate with the same slave device using I2C read,write which can't be done from ARM. This was achieved by the ARM side first doing the code download and sending a message to the DSP notifying the same. Upon receiving the this message, we pinmux the I2C bus from the DSP(given below) and carryout some periodic I2C transactions by pinmuxing the bus opening the bus performing read/write and closing the bus on each transaction. (Note: The ARM doesn't do any transactions after this to avoid conflict over the bus) (PINMUX from DSP) regVal = 0x60002; ((CSL_padRegsOvly)CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_GPIO6_10 = regVal; regVal = 0x60002; ((CSL_padRegsOvly)CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_GPIO6_11 = regVal; CSL_l4per_cm_core_componentRegs *l4PerCmReg = (CSL_l4per_cm_core_componentRegs *) CSL_MPU_L4PER_CM_CORE_REGS; CSL_FINST(l4PerCmReg->CM_L4PER_I2C3_CLKCTRL_REG, L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C3_CLKCTRL_REG_MODULEMODE, ENABLE); while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C3_CLKCTRL_REG_IDLEST_FUNC != CSL_FEXT(l4PerCmReg->CM_L4PER_I2C3_CLKCTRL_REG, L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C3_CLKCTRL_REG_IDLEST)); It is observed that the I2C read and writes are not consistent. We saw that 10 out of 100 write resulted in it failing almost 10-20 times with I2C_STS_ERR_TIMEOUT and the read are even worse with almost 10-30 read fails with I2C_STS_ERR_TIMEOUT. We then tried to debug it by doing the some read transactions and capturing it using a logic analyzer to see what was going wrong and following was observed, Code download from DSP and read from DSP it was seen that the delay between the write and read frame varies from 50-600 us. No fails seen out of 1000 reads. Code download from ARM and read from ARM it was seen that the delay between the write and read frame is around 40-60 us every time. No fails seen out of 1000 reads. Code download from ARM and read from DSP it was seen that the delay between the write and read frame varies from 5-600 us, at times whenever read took <20us we saw that the read failed with the clock stretching untill timeout. we noticed a peculiar observation from the captures, was that there is no clock stretching just after the address read block from ARM but it does stretch every time from DSP. Conclusion If we were to perform the read from the same core where the code download happened the read never failed. When the i2c peripheral is shared i.e., we were to perform the read from the DSP core and the code download form ARM read becomes inconsistent and fails. ideally the code download and read/write transactions should happen in the DSP but as mentioned in the link above we are not able to do it because the timing is inconsistent taken to download from DSP and hence download was moved to ARM and read write transactions done from DSP because it required do so. I2c driver configurations from DSP ad follows, bus_no = 2; i2c_cfg.enableIntr = true; I2C_socGetInitCfg(bus_no, &i2c_cfg); I2C_socSetInitCfg(bus_no, &i2c_cfg); /* * AM5 DSP does not have a default Xbar connection for I2C * interrupt, need the following Xbar interrupt configuration */ /* Use reserved DSP1_IRQ_86 for I2C bus 5 */ CSL_xbarDspIrqConfigure(DSP_INSTANCE, CSL_XBAR_INST_DSP1_IRQ_86, CSL_XBAR_I2C5_IRQ); /* Use reserved DSP1_IRQ_87 for I2C bus 3 */ CSL_xbarDspIrqConfigure(DSP_INSTANCE, CSL_XBAR_INST_DSP1_IRQ_87, CSL_XBAR_I2C3_IRQ); I2C_init(); I2C_Params_init(&i2cParams); i2cParams.bitRate = I2C_400kHz; i2c_bus_handle_st[bus_no].i2c_handle = I2C_open(bus_no, &i2cParams); we are using ti provided I2C_Transfer to read/write from DSP and ioctl for I2C transfer from ARM. bios version: 6_52_00_12 pdk ver: pdk_am57xx_1_0_7 IPC version: 3_47_00_00 Thanks Ranganath
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Forum Post: Importing onnx model through Import tool
Dear Sir, I converted the Tensorflow model to onnx model, now i want to import the same converted model through TIDL Import tool to generate .bin files. I have gone through TIDL Deep Learning user guide, but I couldn't find any reference for this process other then Tensorflow and Caffe models. Kindly help me in this. Thanks and Regards, Shivansh Agnihotri
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Forum Post: TDA2EVM5777: TIDL learning lib issue in building , how to use vcvarsall.bat
Part Number: TDA2EVM5777 Hi everybody , problem was found during the Building of source on host emulation(section 3.5 of TiDeepLearningLibrary_UserGuide.pdf ) Unclear instructions on how to use vcvarsall.bat (section 3.5.2 of TiDeepLearningLibrary_UserGuide.pdf) . could you kindly give proper options to the bat file to use to do right instruction ? beste regrads Carlo
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Forum Post: TMDSICE3359: ICEv2 factory settings
Part Number: TMDSICE3359 Hello, I 've few question : -What is the Kernel of AM3359 ? (Is it a Linux RT, Linux or TI-RTOS kernel?) -And what is the pre installed Operating System on this processor? -And I need to change the OS of this processor if we use the Processor SDK Linux RT, the Processor SDK Linux or the Processor SDK RTOS? Thanks. Best regards, Florian
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Forum Post: TDA2EVM5777: issues in rebuilding TIDL import tool both using command and bash file
Part Number: TDA2EVM5777 Hi everybody , In this page : https://e2e.ti.com/support/processors/f/791/t/689876 is mentioned that by updating the "tidl_tfImport.cpp" and re-building the import tool in the release package we can modify or add layers. We tried to rebuild the import tool as described in the TIDeepLearningLibrary_UserGuide.pdf (section 3.6.1) . I get errore both on command and on bash(Please visit the site to view this file) ( see screenshot attached ) .How can I proceed ? I m on WIN10 64 bits best regrads Carlo
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Forum Post: RTOS/AM5728: sys_nirqx function for SMP
Part Number: AM5728 Tool/software: TI-RTOS Hello, TI Experts, Our customer sent us additional questions about sys_nirqx function of AM5728 from the below E2E thread. https://e2e.ti.com/support/processors/f/791/p/779630/2885183#2885183 They can create their program to use sys_nirq1 and sys_nirq2 on A15_0 like below statements. Thank you ! >hndHwiIrq1 = Hwi_create(39, intProcIrq1, NULL, NULL); >hndHwiIrq2 = Hwi_create(151, intProcIrq2, NULL, NULL); They tied to improve their program by using SMP function with A15_0 & A15_1. And they said they can also success to run sys_nirq1 and sys_nirq2 function with only *.cfg fie modification like below; - BIOS.smpEnabled = true; Question: - Are thee any problem by using NULL parameter like below? >hndHwiIrq1 = Hwi_create(39, intProcIrq1, NULL, NULL); >hndHwiIrq2 = Hwi_create(151, intProcIrq2, NULL, NULL); - Are there any additional code modification by using sys_nirq1 and sys_nirq2 function with SMP? - Could you tell us the recommended way or sample code by using sys_nirq1 and sys_nirq2 function with SMP? Best regards,
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