- Windows 10 64-bit - TwinCAT 3.1 (3.1.4022.2) - CCSv7.2 - pdk_am335x_1_0_8 - PRU-ICSS-EtherCAT_Slave_01.00.05 - SDK 04.01.00.06 my steps as follows: 1) use Show Real Time Ethernet Compatible Devices and install (the realtek PCIe GBE Family Controller) connected to the ICE. (note: green LED3 and yellow LED4 was on) - Go to I/O – Confi guration > I/O Devices – right click and select Scan Device. You will see a list of Ethernet adapters on your system, with a tick next to the adapter connected to the ICE. Choose OK. Device n (EtherCAT) will be added to I/O devices. However, after scan for boxes like shown below, there is no BOX n(TIESC-001) there are some warning as folloes: init15\IO: set state TComObj PREOP OP: Device Device 1 (EtherCAT Automation Protocol) (set to SAFEOP) >> AdsError: 1792(0x700,") 'TCOM Server' (10): PREOP to SAFEOP of 'Device 1 (EtherCAT Automation Protocol)' (0x03010010) failed - 'device error' 0x98110700 I always thought it was a question of network card drivers The network card I use is realtek PCIe GBE Family Controller Supported Network Controller by Beckhoff Ethernet Driver was not contain realtek PCIe GBE Family Controller and then i change PC use AR8162/8166/8168 PCI-Ethernet Controller (NDIS 6.20) The result is the same as above could you give me some advice?
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Forum Post: RE: PROCESSOR-SDK-AMIC110: EtherCAT Slave patch file
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Forum Post: RE: Is this understanding of outQ and quantization outputs correct?
Hi Praveen, Sorry if this wasn't clear. Yes I converted the TIDL outputs to float with OutQ/256 and also transposed the axes (0,1,2 -> 1,2,0) to make them identical to TF axes order. The outputs still do not match. To make the test simpler, I removed batch norm as well. So now I have a single conv + relu layer on both sides and outputs still do not match. Attaching the new relevant files here: drive.google.com/open One more thing is that I added inElementType=0 as well (as inputs are unsigned) but they don't match as well. (Included outputs for both cases in the above link). This time the TIDL o/ps are converted float values (divded by OutQ/256 = 628/256). As you can see, the outputs are nowhere close. I also checked the inputs to the convolution: both the trace_dump_0_416x416.y and the actual inputs to the refConv2DProcess() are proper (I checked by single stepping through the code in Visual Studio). It would be a great help if you can look into what's going on here. Thanks, Bhargav
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Forum Post: RE: TDA3XEVM: edge detect sample build, could not run on D3Engineering Starter Kit
Hi, I am using D3 Starter Kit. And the camera is connected to VIN4. Below is the setup.
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Forum Post: RE: AM5726: Multiple OS support
Hi Eric, Thank you for your response. I understand that if customer use the TI-RTOS for all cores (A15, M4, PRU-ICSS), they could refer the IPC example. Is my understanding correct? If I get more questions, please let me confirm them. Best regards. Kaka
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Forum Post: RE: Linux: Kernel Crash on USb suspend
Ravikiran, Linux kernel v4.9 added runtime power management in musb/cppi drivers, there might be a bug which causes the crash you saw. Let me first try to reproduce it on my side and understand why the crash happens. Can you please explain why you want to remove musb_dsps driver before entering low power mode?
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Forum Post: AM3352: Algorithm for NAND ECC calculation
Part Number: AM3352 Hi, I have the same request to calculate oob data from raw images. The generated images will then be used by a company providing IC programming service. Could you help sort this out ? cheers, Edison
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Forum Post: RE: TDA3XEVM: Why not change the MCSPI_XFERLEVEL value ?
Hi, I think that the explanation of issue is poor. The packet size of wrong case is (33Byte~64Byte) what i said before. The packet size of (1Byte~32Byte) working very well. In the Wrong case, 2. Wrong case (TX, RX each 33Byte) mcspiCfgPrms.spiHWCfgData.fifoRxTrigLvl = 33 ~ 64; mcspiCfgPrms.spiHWCfgData.fifoTxTrigLvl = 33 ~ 64; SoC SPI-1 RX ==> ---- Normal Packet(32Byte~64Byte)---- Normal Packet(32Byte~64Byte) ---- Normal Packet(32Byte~64Byte) ---- Normal Packet(32Byte~64Byte) ---- Normal Packet(32Byte~64Byte) ---- SoC SPI-1 TX ==> ---- Normal Packet(32Byte~64Byte) ---- Wrong Packet(32Byte~64Byte) ---- Normal Packet(32Byte~64Byte) ---- Wrong Packet(32Byte~64Byte) ---- Normal Packet(32Byte~64Byte) ---- And, when i read the register, the WL size is 8bit. 0x4809812C MCSPI1_MCSPI_CHxCONF_0 0x4809812C 180603C0 Plz recheck the issue. Regards, Lee
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Forum Post: RE: J6EVM5777: How to flash MLO and u-boot binaries on QSPI memory through UART3 boot mode on DRA7xx?
Thanks Rishabh for support.
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Forum Post: RE: J6EVM5777: How to change the clock of the SD Card (MMC1) in Processor SDK 3.4?
My issue is resolved. Thanks.
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Forum Post: RE: Linux/DRA745: How to enable debug print into u-boot?
Thanks Shravan for support. -Chetan
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Forum Post: RE: Linux/DRA77P: DRA7XXP bb2d support
Hello Gowtham Thanks for you reply From previous experience , GPU driver will cause kernel crash when enable Power managerment ,In some testcase of 500 hours unit test And ,Yes ,we use 2GB , For current now ,we get this work , with 0x80000000 and powermanager on just be curious , will you debug the driver with powermanager off ? opp might be not needed for our info+ cluster system Thanks
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Forum Post: RE: CCS/AM4377: Boot issues
This problem is due to the fact that the reset signal of the AM4377 has been pulled down by the reset chip and this problem has been solved. Thank you. Best regards.
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Forum Post: TDA3XEVM: TMS320C64x+ DSP cache configuration
Part Number: TDA3XEVM Hi, I am doing a monitoring function to monitor the dsp cache configuration. By reading through the memory browser, I figure out our current system dsp cache configuration as follow: I checked app.cfg and I only found ti_ sysbios _family_c66p_Cache.initSize.l2Size = ti_ sysbios _family_c66p_Cache.L2Size_128K which configure the L2 cache . I cannot seem to figure out where we are configuring L1D and L1P cache. Can I know what are the ways to configure DSP cache?
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Forum Post: AM4372: About kernel and uboot am437x-gp-evm.dts
Part Number: AM4372 Hi all, Can I access emmc from u-boot? "am437x-gp-evm.dts" is in the following two folders. ti-processor-sdk-linux-am437x-evm-04.03.00.05/board-support/linux-4.9.69+gitAUTOINC+9ce43c71ae-g9ce43c71ae/arch/arm/boot/dts ti-processor-sdk-linux-am437x-evm-04.03.00.05/board-support/u-boot-2017.01+gitAUTOINC+c68ed086bd-gc68ed086bd/arch/arm/dts The dts file on the kernel side has emmc pin settings. However, the dts file on the u-boot side has no emmc pin setting. Therefore, I'd like to know if there is a reason why emmc can not be used on uboot side. Best regards, Sasaki
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Forum Post: TDA2: DDR DQ signal swapping rules
Part Number: TDA2 In the DDR2/DDR3 interface design, can we swap DQs with in the same byte? is there any rules on this? such as dq0 swapped with dq3 dq2 with dq7, etc Thanks Jianming
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Forum Post: RE: Linux/PROCESSOR-SDK-AM57X: Duplicate screen support
I hope the latest weston will be integrated into the next LINUX_SDK release. Or, you can help me to build the latest weston to support it. Thank you.
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Forum Post: Compiler/TDA2: Fail to linking openCV file (objdetect)
Part Number: TDA2 Tool/software: TI C/C++ Compiler Hi experts, I'm trying to implement application code that is using openCV However, when I try to compile it, linking error occurs ( undefined reference error ) I checked header file declaration and it exists in proper directory It seems that using has a problem. Using and works well... Please help me.. application.cpp--------------------------------------------------------------------------------------------------------------------------------------- .. #include "DMS_Algo_Typedef.h" ... void* openclDilationThreadFunc(void* args) { sDMS *DMS = new sDMS; .... } DMS_Algo_Typedef.h ------------------------------------------------------------------------------------------------------------------------------- typedef struct sFaceDetector { sParam_faceDetector param_init; sParam_faceDetector param; cv::Rect faceROI; cv::Mat faceRoiImage; cv::CascadeClassifier classifier; cv::Rect face; unsigned char fFaceDetect; } sFaceDetector; ... typedef struct sDMS { // Face detection sFaceDetector faceDetector; // Eye detection sEyeDetector eyeDetector; // Object management sGlobalObject objects; // Image cv::Mat inputFrame; cv::Size imgSize; // State unsigned char detectState; } sDMS;
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Forum Post: RE: CCS/AM5728: System trace
Tom, yes, we have connected to an EVM with CCS and executed the GEL files. For a custom board, how to go ahead about it. BR satya
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Forum Post: RE: CCS/AM5728: System trace
Satya, You stated that the processor subsystem was identical to the EVM. Therefore, you need to repeat the exact same procedure. If you cannot, then you need to be explaining to us what is different in the processor subsystem of the custom design from the EVM design. Tom
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Forum Post: RE: TDA3XEVM: TMS320C64x+ DSP cache configuration
Hi Myat, The default behavior, when DSP is pulled out of reset, is that the L1P and the L1D caches are on and their size is set to 32 KB. The init size from BIOS is also set in the same way: bios_X_XX_XX_XX\packages\ti\ sysbios \family\c66\Cache.xdc /*! Default sizes of caches. * @_nodoc */ config Size initSize = { l1pSize: L1Size_32K, l1dSize: L1Size_32K, l2Size: L2Size_0K }; Thanks and Regards, Piyali
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