Hello Steve, The following message is the console output when i flash the qspi, i loaded the u-boot.bin from the SD card. When I took the SD card and tried to boot from the qspi, there was no output. U-Boot SPL 2017.01-00458-gccd1c34-dirty (May 12 2018 - 08:40:23) Trying to boot from MMC1 SPL: Please implement spl_start_uboot() for your board SPL: Direct Linux boot not active! reading u-boot.img reading u-boot.img reading u-boot.img reading u-boot.img U-Boot 2017.01-00458-gccd1c34-dirty (May 12 2018 - 08:40:23 +0800) CPU : AM437X-GP rev 1.2 Model: TI AM437x SK EVM DRAM: 1 GiB PMIC: TPS65218 NAND: 0 MiB MMC: OMAP SD/MMC: 0 reading uboot.env ** Unable to read "uboot.env" from mmc0:1 ** Using default environment Net: not set. Validating first E-fuse MAC cpsw, usb_ether Hit any key to stop autoboot: 0 => mmc rescan => fatload mmc 0 ${loadaddr} u-boot.bin reading u-boot.bin 475850 bytes read in 134 ms (3.4 MiB/s) => sf probe 0 SF: Detected mx25l51235f with page size 256 Bytes, erase size 64 KiB, total 64 MiB, mapped at 30000000 => sf erase 0x0 0x80000 SF: 524288 bytes @ 0x0 Erased: OK => sf write ${loadaddr} 0x0 0x80000 device 0 offset 0x0, size 0x80000 SF: 524288 bytes @ 0x0 Written: OK => Best regards, Rita
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Forum Post: RE: Linux: AM437x QSPI boot issue
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Forum Post: Linux/AM4378: UART read fails
Part Number: PROCESSOR-SDK-AM437X Tool/software: Linux Hi sir: could you give me a hand for my trobules? For use the proccessor AM437X uart4,using the devicetree am437x-sk-evm.dts in SDK 04.03.00.05, I have MUX the uart0_ctsn and uart0_rtsn pins in mode 1 for uart4_rxd and uart4_txd .The configration of the pinmux is as follow picture.But when I use the system call function " open / close and read/write" to construct a serial communication. It's cames about that there is signals in the master's TXD and also there is signals in the slaver's RXD ,it comfirmed by the oscilloscope. But I can't have the data transmited by the master TXD by using the system call function "read" to operate "/dev/ttyS4" , the slaver's uart4. The code is also attached as below. I'm appreciate for your reply . The code:
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Forum Post: RE: RTOS: Sysbios boot
Hi Guy, I experimented with removing components and changing entry points, and then talked with the original developer of the dual-core/SMP implementations. The Core module is used in many places, both for synchronizing behavior between the cores, and for partitioning resources (e.g., vector tables, CTM timer IDs, interrupts). And the common entry point (in the .ducatiBoot sections defined in the Core* assembly files) efficiently starts both cores from the common reset vector, branching each to the appropriate core-specific entry point in the appropriate vector table (placed at precise locations in shared memory). And GateDualCore provides the primary mechanism to arbitrate access from both cores to common shared memory, AMMU, and for unicache operations. GateDualCore is also used for implementing power management of the cores, synchronizing re-boot/resume after the power-gated suspend state. There really isn’t a clean way to remove only portions of Core, or to change the primary entry point without other very significant modifications and loss of functionality. This is not something we’d recommend. It might be best to ‘start over’ for your specific dual-core use case rather than take that approach. All that said, I’m wondering why you need to make such significant modifications. If you continue to use Core and the pre-defined entry point, you will also be able to continue to use the available Timer and Timestamping services in your NDK app on Core 0. And your other app on Core 1 can be “mostly” bare metal, with the exception of the minimal startup code in the Core* asm files to launch the core to the appropriate entry point for that application. Is there some reason you can’t use the existing dual-core infrastructure to run your larger NDK-based app on Core 0, and your other app (that doesn’t interact with Core 0) can run independently after startup on Core 1? Thanks, Scott
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Forum Post: RE: Linux/AM5728: Booting from mSATA
Hi Steve, Will you tell me what changes you made in bootargs so it loaded the rootfs from mSATA? BR Vijay Patil
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Forum Post: RE: RTOS: Sysbios boot
Hi Thanks. I basically managed to replace the .ductiboot with my custom boot and it seems to be working (still needs further checking). i see no reason why i cant do this as the ductiBoot only holds the very first startup code which is what i am replacing - this will enable me more control and also make sure that both cores (baremetal and sysbios has the same startup code - as it must be the same since both start from the same location). i still kept the Core module and the Gates (even though i am not sure it is really necessary) so everything else i suppose should be functioning the same. Also for our application,even though it is not a must, it makes more sense for example that the first core is core1 (NDK also runs on core1) (this is due "historic reasons" (before "my time") and reversing it now is not really an option). I was hoping there is a better/simpler way to achieve what is have done since i assumed that this XDC design is supposed to be fully customized, but i still encountered some things i had to leave as is but make them ignored. i.e. from some reason, even though i was able to add a function to the Startup First and Last Functions list i was not able to modify replace an automatically inserted function - once i tried it i seems to cause it to remove everything else from both lists also and i am not sure what other impact i may have (no idea why it behaves like this). for example i wanted to remove the function that for example clears the ducati core1 wait flag since it is no longer needed but could not accomplish this so i had to keep it (and as a result keep that flag too ). As for the entry point, since i could not find a way yet to add something to the created linker file (Can you help with this) so in the meanwhile i found that there is an option to replace the linker template being used, which allowed me to add the new entry point. i also wanted to try to avoid having the reset vectors hard coded as fixed addresses (0x800 , 0x400) so i changed it to be linker dependent. the custom file (the one that replaces the ducatiBoot asm file) is basically based and very similar to the original file but with a few minor modifications. Do you see any problem with the way i described above (i.e. something you said probably wont function correctly when trying to change that should check)? If you still think and point out the reason that it will cause something to be really wrong, I can try and make it work with current .ductiboot - but i really rather not (again i mainly replaced only the initial asm file which is also very similar and the rest should be pretty much the same) Thanks Guy
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Forum Post: RE: AMIC110: EtherCAT errata PINDSW-1531
Hi Paula No,slaves don't use DC mode. Kanae
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Forum Post: RE: RTOS: access linker symbols from RTSC XDC config file
Hi, I thought i have answered the question but i might have misunderstood it. I would like to know if and how to set a variable in the .cfg file (both when it is a variable of some module and when it is a variable i create globally ) and make its value equal to the value of a symbol that is defined in the linker command script (not a defined constant like #define) . then i would like to know how can i also access that variable from the C code. I am not that familiar with RTSC and its modules so i could still probably misunderstanding what you were asking. Thanks Guy
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Forum Post: RE: AM5716: IDK Schematic
The factory team have been notified. They will respond here.
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Forum Post: J6EVM5777: Error :: SF: Unsupported flash IDs while executing "sf probe 0" uboot command
Part Number: J6EVM5777 Hello All, For our custom board, when we execute uboot command (sf probe 0) in uboot prompt, we observed below error: SF: Unsupported flash IDs: manuf 20, jedec ba19, ext_jedec 1044 Failed to initialize SPI flash at 0:0 (error -93) And we cross verified flash IDs: manuf 20, jedec ba19, ext_jedec 1044 with our QSPI flash memory's datasheet. Note: 1. We tried same command on J6 EVM board and we got below information: SF: Detected S25FL256S with page size 64 KiB, total 32 MiB, mapped at 5c000000 Please give suggestions. OR any u-boot source code changes are required for our custom board? Thanks, Chetan
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Forum Post: AM5728: CMEM issues
Part Number: AM5728 Now I have confirmed the starting address and address range of DDR，But how to get the address of DSP_CMEM_IOBUFS ？ please to help me
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Forum Post: RE: AM5716: IDK Schematic
Hi Lawrence, You stated that you imported the DSN database. Does that mean you are using a schematic package other than Orcad? The total number of symbol parts I see for the AM5718 in the IDK schematic is 27. Regards, Bill
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Forum Post: RE: AM5716: IDK PCB layout
Hi Lawrence, The AM5718 EVM does use blind and buried vias. In the drill drawing above you can see that there is a drill chart for Top to L2, a drill chart for L2 to L3, a drill chart for L3 to L10, a drill chart for L10 to L11 and a drill chart for L11 to Bottom. If you highlight all the layers the drills will not line up since these drill charts are treated separately. I do see alignment when I turn on layers 3 to 10. Which agrees with the tables above. Regards, Bill
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Forum Post: CCS/AM3358: JTAG error connecting to PRU
Part Number: AM3358 Tool/software: Code Composer Studio I use CCS Studio : 8.0.0.00016 on Linux Mint 16.04. I read this , this and this . I imported the PRU_Hardware_UART project from the support package and this is my target configuration file: and selecting PRU_0: Are these gel files correct ( I have not changed them ) ? Clicking on Test Connection seems to succeed: [Start: Texas Instruments XDS110 USB Debug Probe_0] Execute the command: %ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -S integrity [Result] -----[Print the board config pathname(s)]------------------------------------ /home/p/.ti/ti/0/0/BrdDat/testBoard.dat -----[Print the reset-command software log-file]----------------------------- This utility has selected a 100- or 510-class product. This utility will load the adapter 'libjioxds110.so'. The library build date was 'Feb 8 2018'. The library build time was '18:25:14'. The library package version is '7.0.188.0'. The library component version is '35.35.0.0'. The controller does not use a programmable FPGA. The controller has a version number of '5' (0x00000005). The controller has an insertion length of '0' (0x00000000). This utility will attempt to reset the controller. This utility has successfully reset the controller. -----[Print the reset-command hardware log-file]----------------------------- The scan-path will be reset by toggling the JTAG TRST signal. The controller is the XDS110 with USB interface. The link from controller to target is direct (without cable). The software is configured for XDS110 features. The controller cannot monitor the value on the EMU[0] pin. The controller cannot monitor the value on the EMU[1] pin. The controller cannot control the timing on output pins. The controller cannot control the timing on input pins. The scan-path link-delay has been set to exactly '0' (0x0000). -----[Perform the Integrity scan-test on the JTAG IR]------------------------ This test will use blocks of 64 32-bit words. This test will be applied just once. Do a test using 0xFFFFFFFF. Scan tests: 1, skipped: 0, failed: 0 Do a test using 0x00000000. Scan tests: 2, skipped: 0, failed: 0 Do a test using 0xFE03E0E2. Scan tests: 3, skipped: 0, failed: 0 Do a test using 0x01FC1F1D. Scan tests: 4, skipped: 0, failed: 0 Do a test using 0x5533CCAA. Scan tests: 5, skipped: 0, failed: 0 Do a test using 0xAACC3355. Scan tests: 6, skipped: 0, failed: 0 All of the values were scanned correctly. The JTAG IR Integrity scan-test has succeeded. -----[Perform the Integrity scan-test on the JTAG DR]------------------------ This test will use blocks of 64 32-bit words. This test will be applied just once. Do a test using 0xFFFFFFFF. Scan tests: 1, skipped: 0, failed: 0 Do a test using 0x00000000. Scan tests: 2, skipped: 0, failed: 0 Do a test using 0xFE03E0E2. Scan tests: 3, skipped: 0, failed: 0 Do a test using 0x01FC1F1D. Scan tests: 4, skipped: 0, failed: 0 Do a test using 0x5533CCAA. Scan tests: 5, skipped: 0, failed: 0 Do a test using 0xAACC3355. Scan tests: 6, skipped: 0, failed: 0 All of the values were scanned correctly. The JTAG DR Integrity scan-test has succeeded. [End: Texas Instruments XDS110 USB Debug Probe_0] In PRU Training: Hands-on Labs , step 9 of Lab1 says: 9. Let’s launch the debugger and load the code! a. Right click the Target Configuration file we just created and select Launch Selected Configuration. There is no menu entry Launch Selected Configuration: I added the startup script to the debug configuration: And when I click Debug, I get: What can I do ? (Note: There is no SDCard inserted and I pressed the Boot button at startup to prevent Linux from booting , only the power LED is lit, no heartbeat blinking ) Thanks and regards Peter
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Forum Post: RE: AM5728: CMEM issues
The IPC experts have been notified. They will respond here.
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Forum Post: RE: AM5726: Multiple OS support
Kaka, All the cores are standalone, you can run different OS on different cores. Also, even running TI OS, you can run customized features on different cores. But running different OS on cores increases the complexity of the system as a whole, because you may need some inter-processor communications, task partitioning, etc among them. TI has IPC solution using TI-RTOS . But if you choose some bare metal, some RTOS, some freeRTOS, you may need to handle this. Regards, Eric
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Forum Post: RE: AM5726: 64-bit atomic memory access from ARM
Carlo, For ARM A15, The TI A15 core supports from TRM. Neon is required to support atomic, it is a compiler option. For C66x, www.ti.com/.../sprab89a.pdf "Scalar variables are aligned such that they can be loaded and stored using the native instructions appropriate for their type: LDB/STB for bytes, LDH/STH for halfwords, LDW/STW for words, and so on. These instructions correctly account for endianness when moving to and from memory." So reading/writing a data up to 64 bits (for C66xx that have the LDDW/STDW) should be implemented as a single load/store, that is atomic. Regards, Eric
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Forum Post: RE: RTOS/AM5728: GPIO driver index mapping
For AM572x TRM, 27.1 General-Purpose Interface Overview. There are 8 GPIOs each with 32-pin, it is indexed from 1. So GPIO1, GPIO2, GPIO3 .... GPIO8. Pin is indexed from 0 to 31. Under GPIO driver pdk_am57xx_1_0_10\packages\ti\drv\gpio\soc\am572x, there is a gpio_soc.c. There is a GPIO_v1_hwAttrs define the 8 GPIO instances, you can see the instance index 0 pointing to GPIO_1, index 1 point to GPIO_2. So, GPIO1_0 is 0, not 32 if you count this way. Also you can see the GPIO LED toggling example, #if defined (idkAM571x) #define GPIO_INTR_LED_BASE_ADDR (CSL_MPU_GPIO2_REGS) #define GPIO_LED_PIN_NUM (0x15U) #endif #if defined (evmAM572x) #if defined (__TI_ARM_V7M4__) #define GPIO_INTR_LED_BASE_ADDR (CSL_MPU_GPIO1_REGS) #define GPIO_LED_PIN_NUM (0x10U) #else #define GPIO_INTR_LED_BASE_ADDR (CSL_MPU_GPIO7_REGS) #define GPIO_LED_PIN_NUM (0x08U) #endif #endif #if defined (evmAM572x) || defined (idkAM571x) || \ defined (skAM437x) || defined (evmAM437x) || \ defined (icev2AM335x) || defined (skAM335x) || defined (bbbAM335x) #define GPIO_BASE_ADDR GPIO_INTR_LED_BASE_ADDR #define GPIO_LED_PIN GPIO_LED_PIN_NUM #endif The GPIO pin is accessed by using GPIO_BASE_ADDR and GPIO_LED_PIN to avoid the confusion. Regards, Eric
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Forum Post: RE: RTOS/AM5716: EDMA memory issue
Hi, Is that correct understanding that: - You have a buffer allocated by Linux, which is a virtual address - There is data come in to this buffer. Is that correct you have a Linux driver for a peripheral (may be MCASP)? and the driver writes the data into this buffer? - You want to use the DSP to move this data to some another locations? But DSP don't know the physical address? How the DSP knows the data come in? MCASP interrupt DSP? Can you use the EDMA in Linux (A53) to move the data? - I don't understand if you have a Linux driver for MCASP to Rx data AND also have a DSP driver for MCASP for interrupt? Can you describe the data IN/OUT path? Regards, Eric
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Forum Post: RE: RTOS/AM5716: UART3 pinmux
Rahul, Thanks a lot! best regards
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Forum Post: RE: Linux/AM5728: Qt QMenu issue
Hi， Margarita，I had test it with SDK04.01, and it was the same result. I will test it with SDK04.03. If you had some progress, please feed back. BR, vefone
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