The factory team have been notified. They will respond here.
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Forum Post: RE: AM5728: PMIC issue with SMPS8
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Forum Post: RE: AM3356: Media Counters in EIP
Hi, Biser Thank you for your reply. It means PRU-ICSS-ETHERNETIP-ADAPTER 01_00_02_00 and Processor SDK 3.3.0.4 for AM335x. Best Regards Hiroyasu
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Forum Post: RE: Linux/AM3352: GPMC multiple read issue
Thanks for your reply, my core question is : is there any issue can influence the continuous GPMC read/write when the single GPMC read/write action all right? Or is there any other people meet the same condition similar to mine? My continous GPMC read/write test code is as bellow: for(iTestStep=0;iTestStep >8; // write write(fdTargetDev, &aucWriteBuf, iAddrLoop); usleep(100); } usleep(2000000); for(iAddrLoop=WRTEST_START_ADDR; iAddrLoop >8)) { printf("error in addr 0x%x!\n",iAddrLoop); printf("\t read data H is 0x%x\r\n", aucReadBuf[1]); printf("\t read data L is 0x%x\r\n", aucReadBuf[0]); } // usleep(1000); } printf("finish the sram test step %d\n",iTestStep); } My single GPMC read/write test code is as bellow: /* Function Name : MvbSram_WriteTest */ void MvbSram_WriteTest(int fdTargetDev) { unsigned char tempbuff[2] = {0}; int iWriteAddr, iWriteValue; printf("\r\nplease input write addr:"); scanf("%x", &iWriteAddr); printf("\r\nplease input write value:"); scanf("%x", &iWriteValue); printf("\r\nstart to write value 0x%x to addr 0x%x.\r\n", iWriteValue, iWriteAddr); tempbuff[0] = (char)(iWriteValue & 0x00FF); tempbuff[1] = (char)((iWriteValue & 0xFF00)>>8); // write write(fdTargetDev, &tempbuff, (size_t)iWriteAddr); return; } /* Function Name : MvbSram_ReadTest */ void MvbSram_ReadTest(int fdTargetDev) { unsigned char tempbuff[2] = {0}; int iReadAddr, iReadValue; printf("\r\nplease input read addr:"); scanf("%x", &iReadAddr); printf("\r\nstart to read value from addr 0x%x.\r\n", iReadAddr); read(fdTargetDev,&tempbuff,(size_t)(iReadAddr)); iReadValue = (int)((tempbuff[0] & 0x00FF) | ((tempbuff[1] & 0x00FF)<<8)); // read printf("\r\nthe returned read value from addr 0x%x is 0x%x.\r\n", iReadAddr, iReadValue); return; }
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Forum Post: RE: RTOS/TI-RTOS: Purpose of TaskP in Profinet
The RTOS team have been notified. They will respond here.
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Forum Post: RE: TDA2XX: How to create new object item in TI's TDA2XX OD module
Hi Manu: I have one question, how to add enum value for new draw object in AlgorithmLink_ObjectDrawOption (vision_sdk/apps/include/alglink_api/algorithmLink_objectDraw.h) ? Regards, Josh
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Forum Post: RE: AM5728: IDK schematics question
The factory team have been notified. They will respond here.
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Forum Post: RE: Linux/AM5728: Kernel internal error
Hi, Doyle , Do you find the reason and the solution? BR, vefone
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Forum Post: AM3359: ARM latencies to PRU
Part Number: AM3359 I want to ask for latencies on AM335X from ARM side to PRU Memories and HW blocks (in cycles). Something similar what you provided for AM335X PRU latencies (best case is enough). Are the latencies same for all AM335X types, when clock speed and other configurations are the same or there is any difference. With best regards Jiri Biel
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Forum Post: TDA2EVM5777: Where can I find the driver which allocates DMABUF?
Part Number: TDA2EVM5777 Hi, I have asked a question in another thread(see the following link). A driver which allocates DMABUF is mentioned in the answers. But I can't find this driver in version 3.0 sdk. e2e.ti.com/.../619507 Can you gives me some information about this driver? Mason Su Best regards
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Forum Post: RE: AM3359: PRU device tree configuration
Hi Nick, Could you possibly hold this topic open for few more days? I've been sick and didn't make much progress... I'm back now and trying your approach now. Regards, Marek
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Forum Post: RE: The ADB of Android O can't work
Hi Vishal, I checked all the related ConfigFS configuration, but it seems that the otg connection is not stale, then it lead to this issue, it show the following message. " [ 10.239101] xhci-hcd xhci-hcd.1.auto: USB bus 3 deregistered [ 10.249111] android_work: did not send uevent (0 0 (null)) [ 10.255982] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller [ 10.263652] android_work: did not send uevent (0 0 (null)) " I attached the kernel log, (Please visit the site to view this file) thanks Jackie
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Forum Post: RE: AM3359: ARM latencies to PRU
The factory team have been notified. They will respond here.
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Forum Post: AM3359: PRU to ARM latency from HW, RTOS and Linux point of view.
Part Number: AM3359 Hello, I want to ask what is the latency of PRU to ARM interrupt for following combinations: 1. Just expected minimum from HW point of view 2. On TI RTOS 3. On Linux RT 4. On Linux With best regards Jiri Biel
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Forum Post: RE: AM3356: DSCP priority for EtherNet/IP
The RTOS team have been notified. They will respond here.
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Forum Post: RE: AM3354: Device frequency
Thank you for your information!
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Forum Post: AM3352: RTC-only wakeup unstable
Part Number: AM3352 Hello, I'm working to implement AM335X RTC-Only mode on our custom boards with AM3352 CPU and TPS65910 PMIC and the device fails to raise PMIC_POWER_EN after rtc-wakeup. I'm using TI-Linux (ti2014.10.00 == 3.14.19) with patched-in support for our board. After initiating RTC-Only powerdown according to TI wiki ( processors.wiki.ti.com/.../Linux_Core_Power_Management_User's_Guide_(v3.14) - exception: using rtc1 as wakeup source because I have to use the pmic-rtc - the power consumption drops for the requested number of seconds via rtcwake. Then the power consumption rises again and I can observe a cold boot on the debug console as it starts up U-Boot. But this lasts only for about 1 second, then the device is switched off again with power consumption dropping to powerdown levels. I determined that the PMIC is responsible for this powerdown. In the datasheet (www.ti.com/lit/ds/symlink/ tps65910 .pdf) it states in chapter 5.22.2 Power Control Timing: --- NOTE: (1) The DEV_ON control bit (set to 1) or the PWRHOLD signal (set high) can be used to maintain supplies on after switch-on sequence, If none of these devices POWER-ON enable condition are set the supplies will be turned off after TdOINT1 delay. --- TdOINT1 is specified to be 1 second on table 5-5. DEV_ON is 0 and PWRHOLD is low after wakeup. This leaves two options: (1) Set DEV_ON = 1 in PMIC to force power supply on. This works and allows full cold boot, but having DEV_ON = 1 prohibits power off for following RTC-Only cycles. Also as soon as DEV_ON is cleared to 0 even after TdOINT1 the device shuts off immediately. (2) Set PMIC input PWRHOLD to high. This input is connected to AM3352 's output pin PMIC_POWER_EN. Right now I'm stuck on option (2) as option (1) is not usable as mentioned. I tried clearing bit PWR_ENABLE_EN in register RTC_PMIC and clearing ALARM2 interrupt status to no avail. I took register dumps of PMIC-RTC and AM3352-RTC on a regular boot and after rtc-wakeup. Please let me know if further information is needed. Thanks for any ideas. Best regards, Michael Krummsdorf (Please visit the site to view this file)(Please visit the site to view this file)
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Forum Post: RE: Linux/AM3351: NAND conflict with UART4
i am using u-boot-2017.01+gitAUTOINC+590c7d7fe1-g590c7d7fe1, linux-4.9.41+gitAUTOINC+e3a80a1c5c-ge3a80a1c5c. i got below logs through uart4 U-Boot 2017.01-00360-gc6c77f9-dirty (Mar 20 2018 - 15:13:35 +0530) CPU : AM335X-GP rev 2.1 Model: TI AM335x BeagleBone Black DRAM: 256 MiB NAND: 0 MiB MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1 reading uboot.env ** Unable to read "uboot.env" from mmc0:1 ** Using default environment not set. Validating first E-fuse MAC Net: No ethernet found. Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc0 is current device SD/MMC found on device 0 reading boot.scr ** Unable to read file boot.scr ** reading uEnv.txt ** Unable to read file uEnv.txt ** switch to partitions #0, OK mmc0 is current device Scanning mmc 0:1... reading /am335x-boneblack.dtb 40718 bytes read in 15 ms (2.6 MiB/s) switch to partitions #0, OK mmc0 is current device SD/MMC found on device 0 3619776 bytes read in 766 ms (4.5 MiB/s) 40758 bytes read in 39 ms (1020.5 KiB/s) ## Flattened Device Tree blob at 88000000 Booting using the fdt blob at 0x88000000 Loading Device Tree to 8df1d000, end 8df29f35 ... OK Starting kernel ... [ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Linux version 4.9.41-ge3a80a1c5c (root@sridhar-ThinkCentre-M73) (gcc version 6.2.1 20161016 (Linaro GCC 6.2-2016.11) ) #1 PREEM8 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [ 0.000000] OF: fdt:Machine model: TI AM335x BeagleBone Black [ 0.000000] efi: Getting EFI parameters from FDT: [ 0.000000] efi: UEFI not found. [ 0.000000] cma: Reserved 48 MiB at 0x8a800000 [ 0.000000] Memory policy: Data cache writeback [ 0.000000] CPU: All CPU(s) started in SVC mode. [ 0.000000] AM335X ES2.1 (neon) [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64960 [ 0.000000] Kernel command line: console=ttyO4 ,115200n8 root=PARTUUID=0001819e-02 rw rootfstype=ext4 rootwait [ 0.000000] PID hash table entries: 1024 (order: 0, 4096 bytes) [ 0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes) [ 0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes) [ 0.000000] Memory: 198316K/262144K available (7168K kernel code, 284K rwdata, 2396K rodata, 1024K init, 280K bss, 14676K reserved, 49152K ) [ 0.000000] Virtual kernel memory layout:
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Forum Post: RE: Linux/DRA77P: XIP boot from 256MB NOR not working after a warm reset
Francesco, could you provide data of the CTRL_CORE_PAD_GPMC_A27 register (address 0x4A0034AC) for the failing case?
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Forum Post: RE: AM3359: EDMA transfer from PRU to DDR3
Hello Bisher, this question was not about of any OS (but we are using some core functionality of Starterware from latest PDK). The question is how DDR3 is working when buffer is located in DDR3 part of memory which is cashed and we tried to transfer the data via EDMA from SharedRAM to the buffer. I need to only know whether it's a need to switch off the data cache for this part of memory to be working or it should work also with data cash switched on and problem is somewhere else. In case that it's a need, I want to ask what is the quickest solution to transfer data from Shared RAM to DDR3. Thank you. Jiri Biel
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Forum Post: RE: AM5716: RTC wakeup signals
Melissa, Any news for this topic? Regards, Patrick
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