Hi Paul,
In general we would like to have least amount of (un-controlled) jitter in the system as possible. If we need jitter, for EMC-reasons for instance, we could revert to Spread Spectrum Clocking to do that in a controlled way.
So basically the peripheral pll is the difficult one, being the only ADPLLLJ. Is it possible to run that one with N=4, M=192 and M2=5? That would give us a reference clock at 5MHz and the same two clocks at 960 and 192MHz as before.
The other 4 pll's could then run with N=0 or 4, and the appropriate M dividers. Only the DDR3 pll would have a slightly different frequency of 305MHz i.s.o. 303.
regards,
Kees