Why do you need to change the clk to kHz range? I assume you need to do this to decrease the ADC sample rate.
My reply below is from the hardware perspective. I cannot comment how this is done in various software drivers.
Increasing the value of the ADC_CLKDIV register decreases the frequency of ADC_CLK. This is one way to decrease the ADC sample rate. ADC_CLK is sourced from OSC0 which is normally connected to a 24MHz crystal.
The FSM sequencer in the ADC provides two programmable delays for each step. Open Delay is used to control when the acquisition begins after the step starts and Sample Delay is used to control the acquisition period. Delays for each of the 16 steps can be configured independently via the respective STEPDELAYx register. Open Delay defaults to a value of zero which causes the acquisition period to begin as soon as the step starts. The start of the acquisition period can be delayed one ADC_CLK clock period for each incremental value of Open Delay. Sample Delay defaults to a value of zero which causes the acquisition period to be equal to two ADC_CLK clock periods. The acquisition period can be extended one ADC_CLK clock for each incremental value of Sample Delay.
The maximum sample rate for the ADC is 200ksps and it takes at least 2 ADC_CLK cycles to perform an acquisition and 13 ADC_CLK cycles to convert the acquired voltage to a digital value. This will allow the ADC to sample a single analog input at 200ksps if ADC_CLKDIV is configured to provide a 3MHz ADC_CLK and the values of Open Delay and Sample Delay are both zero. So increasing the value of Open Delay and Sample Delay can also be used to reduce the ADC sample rate.
Regards,
Paul