Forum Post: Cache and store buffer maintenance in cortex-a8!

Dear All,

Technical data sheets for the ARM7500FE  and ARM7100 say that:

"In the ARM Processor the cache will be searched regardless of the state of the C bit, only reads that miss the cache will be affected."

Now the question is that whether it holds for the cortex-a8 processors family or not?

The other question is that when switching the ARM domains whether the store buffer gets automatically drained or we have to use the barriers for this?

Many thanks in advance.