Ultimate suitability for a particular peripheral device, in this case the Marvell switch, is the responsibility of the customer as we can't claim expertise in another vendor's part. I have not seen the particular device used with ours, but a cursory review of their datasheet reveals nothing that jumps out at me as a problem. It does appear to support "R/MII PHY Mode" on more than one port which allows for the AM335x-supported MAC-to-PHY connection. Also, standard IEEE 802.3u clause 22 support for MDIO makes implementation much easier than having to bit-bang a custom interface.
Connecting both "PHY"s to the same MDIO channel is fine. A single MDIO bus with multiple devices is the typical topology for this interface.
I thought I'd note that if you plan on supporting Ethernet boot, that you must (practically) connect a PHY that supports a hardware-strap option for internal delay on both Rx and Tx channels. I say practically because the other option is to introduce the required delays via ~10" of extra trace length on both clocks, which very often is not possible. If you don't plan on supporting Ethernet boot, this isn't an issue, but if you do...please refer to the AM335x Errata/Advisory 1.0.10 and search this forum for "internal delay" for more details. The issue is well documented here.
Whichever device you choose to connect to AM335x, you must perform a timing analysis to ensure that the devices on both sides of the interface are able to co-exist from an electrical timing (setup/hold/delay) perspective. As this is affected by trace length, I'd recommend verifying gross (ballpark) timing when choosing the PHY and then again when actually doing the layout.
On a more personal note, the publicly available datasheet for the Marvell switch is marked "Preliminary" and dated 2008. If this were my design, I'd be concerned about long-term availability of the part.