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Forum Post: AM3352 DDR Config

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Hi,

I am new to DDR. I have a doubt.

1)Suppose if one configure a register like

#define DDR2_EMIF_TIM1 0x0666B3D6
#define DDR2_EMIF_TIM2 0x143731DA
#define DDR2_EMIF_TIM3 0x00000347
#define DDR2_EMIF_SDCFG 0x58805232 
#define DDR2_EMIF_SDCFG2 0x08000000

what does it imply? Is that represents a configuring the bits in that particular register?

2)Here is the piece of info available in EMIF configurations tips for DDR2.

In that , DDR_IO_CTRL (@0x44E10E04) is mentioned. what it implies? Is that a mapping addess? How to code the particular register?

Control Module Registers

Some DDR configuration involves Control Module registers which are outside of the DDR controller and DDR PHY modules. Here is a summary of their configuration.

  • DDR_IO_CTRL (@0x44E10E04) - Controls the I/O mode for the DDR I/Os.
    • MDDR_SEL - this puts the I/Os in CMOS mode (for LPDDR operation, set to 1) or STL mode (for DDR2/DDR3 operation, set to 0)
  • VTP_CTRL (@0x44E10E0C) - controls the VTP (Voltage-Temperature-Process) compensation for the DDR I/Os. VTP calibration should occur after the DDR PLL is setup, but before any other DDR controller or DDR PHY configuration is performed. VTP calibration should be performed at power up and each time the DDR controller is re-initialized. Here are the steps to perform VTP Calibration:
    • Set ENABLE to 1 to enable VTP
    • Clear CLRZ to 0 to clear out flops and start count again
    • Set CLRZ to 1 to complete the toggle of CLRZ
    • Check for VTP ready bit. If 1, the training sequence is complete

Thank You!

Help me with some ideas!


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