Forum Post: RE: AM355x GPMC_CLK (V12) Pin

Hi Biser,

thanks for the reply. Our software and FPGA designer here needs the GPMC_CLK exactly equal to the Master Input Clock, which in our case is 25Mhz. Not having same phase and jitter is ok. They just need to be exactly same frequency.

thanks again for the help,

irwin weiss

MRV communications