Hi Emilio,
I tried forcing output to tv and I can see the error you are getting.
Furthermore, I did some experiments with DPI output, and the scaling requirements you have cause a sync loss and fifo underflow to occur, and in this case we do get the required fclk needed for the scaling due to a different clock source being used.
It looks very likely that downscaling at this higher resolution by this factor is simply 1) beyond what the PLL that the clocking infrastructure uses to supply fclk for tv output can handle and 2) beyond the bandwidth limits of what it takes to keep the 1kB fifos the feed the video planes in good order.
At this point, I would say the best course of action to take would to find another way to do the downscaling you need without doing it all at once in the video plane. Perhaps using the 2nd video plane in writeback mode as a 1 stage scaling, and then your display video plane in output mode to do the final amount of scaling could work for your application.
Regards,
Josh