Hi Andreas,
Quoting from another post:
"....If you look at section B4.1.83, you can find the Instruction Set Attribute Register 0, VMSA. Divide_instrs, bits[27:24] indicates the implemented Divide instructions. Permitted values are:
0b0000 None implemented.
0b0001 Adds SDIV and UDIV in the Thumb instruction set.
0b0010 As for 0b0001, and adds SDIV and UDIV in the ARM instruction set.
Using Code Composer, I connected via JTAG to an AM335x and read back this register: Instruction Set Attribute Register0: 0x00101111 This indicates that SDIV and UDIV are not implemented since bits [27:24] = 0".