Forum Post: DDR3 Write Enable Connection

I'm currently making a schematic for the AM3352 with dual x8 DDRs.  I want to confirm that I'm hooking this up correctly.  

Is the DDR_DQM[1:0] omitted for this configuration since there are two unique parts in lieu of DDR_WEN?  When looking at the datasheet, I see that DQM[1:0] are labeled as "Data WRITE ENABLE/DATA MASK FOR DATA[x:y]" and the DDR_WEN is "DDR SDRAM WRITE ENABLE OUTPUT]  

Do I use only ddr_wen? Or do I use DDR_DQM[1:0] for each IC?