The behavior is the same with that change to SDRAM_CONFIG.
Am I correct in believing that as I have the EMIF configured, the address as viewed in CC Studio or in the software should will be translated as follows:
row address | bank address | column address
So if I were to write to byte address 0x80000008 in CC Studio, it would write to row 0, bank 0, column 4 (since it gets translated from a byte address to a word address). Correct?
I have been looking at transactions on a logic analyzer. It appears the memory controller is sending the row address and bank address correctly to the DDR chip. However, changing bits 1 through 3 of the byte address in CC Studio (which correspond to bits 0 through 2 of the word address) does not impact the lower 3 bits of the column address. I can make the 4th bit change of the column address change, but not the 3rd bit. Any ideas?