Part Number: TDA2SX HI master: sdk: processor_sdk_vision_03_05_00_00 my board boot as linux target, RTOS IPU hmdi to VGA, the receiving end has been connected to VGA display， HDMI does not output, The customer needs the same HDMI to be divided into two HDMI channels through ts3dv642 , namely hmdi to VGA and HDMI to LVDS (ds90ub929). When switching to LVDS, HDMI can output signals (measured by oscilloscope). However, when switching to VGA, M4 IPU cannot output signals. If the HDP pin is pulled high or low, or from low to high, the IPU M4 cannot output the signal. Found by printing the HDMI register. When there is no output signal, the value of the HDMI_WP_ PWR_Ctrl register is 0x9a. When the signal can be output when the hmdi is converted to LVDS, the value of the HDMI_WP_ PWR_Ctrl register is 0XAA. The values of other registers are the same. I don't know how hmdi can output signals when the receiver is VGA. HDMI_WP_ PWR_Ctrl: Reserved reserved. R 0x0 7:4 reserved see device HDMI addendum for bit description R 0x0 3:2 PLL PWR CMD command for power control of the HDMI PLL control RW 0x0 Module 0x0: command to change to off state (PLL PWR CMD off signal) 0x1: command to change to on state for PLL (dcoclk Is power down (PLL_PWR_CMD_On_HS_CLK signal) 0x3: command to change to on state for PLL (no Dcoclkldo / clkdcoldo clock output to the hdmiphy (PLL_PWR_CMD_On_Div signal) 0x2: command to change to on state for PLL (PLL PWR CMD on all signal) 1:0 PLL_PWR_Status of the power control of the HDMI PLL control R 0x0 Module 0x0: HDMI PLL control module in off state 0x1: HDMI PLL control module in on state for PLL 0x3: HDMI PLL control module in on state for PLL (no Clock output to the hdmi-phy) 0x2: HDMI PLL control module in on state for PLL
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