Hideaki, it mainly becomes a reliability issue and depends on how different the voltages are between two different voltage domains. See figure 5-4. It is difficult to predict the effect, as we only give guidance to guarantee the reliability specified in the datasheet. Note that the datasheet gives some flexibility in power when using the PMIC. See this note: The power down sequence shown is the most general case and is always valid. An accelerated power down sequence is also available but is only valid when porz is asserted (low). This accelerated power down sequence has been implemented in the companion PMIC that is recommended for use with this SOC. The accelerated sequence has porz go low first, then all 3.3V supplies simultaneously second, core supplies, DDR supplies and DDR references simultaneously third and all 1.8V supplies simultaneously last. Regards, James
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