Hi Paul,
Thank you for your reply.
Here is the comment from PMIC support team: http://e2e.ti.com/support/power_management/pmu/f/200/t/202260.aspx
They chose to stagger the DDR3 rail and the 1.8V rail by 1ms until the 1.8V rail comes up after the DDR3 rail comes up.
Best regards,
Daisuke