Part Number: 66AK2G12 Dear All, we have a custom board with an 66AK2G12 where we interface some chips via GPMC. The PDK I am using is "pdk_k2g_1_0_13" from the latest SDK "processor_sdk_rtos_k2g_5_03_00_07" The TRM I am referring to is "SPRUHY8I January 2016–Revised March 2019" After searching for details I am left with some open points to clarify: For a NOR flash with non-multiplexed data and address lines, is the addressable space really limited to 2KB in size? In the forums I found that for some other devices this statement is only wrong in the TRM but not true for the chip. Please can you tell me what is correct? In the example code located at "pdk_k2g_1_0_13\packages\ti\board\diag\nand\src" there is a call "GPMCLimitedAddrDevSupportConfig" But the affected bit 1 in the GPMC config register is defined as "reserved" in the TRM Please tell me if it is relevant to clear the bit to not have the 2KB address limitation I have problems to understand the address decoding We have a CPLD connected to A1-A3 D0-D7 on CS1 so what is the physical address to be used? There are 8 valid addresses 0x00000000-0x0000000E Are these settings for GPMC_CONFIG7 correct? base: 0b000000, mask: 0b1111 (16MB) So this reserves address range 0x00000000-0x01000000 for CS1 and only 8 addresses are used What is the address I have to use in my code? The GPMC_0_DATA is located at 0x30000000-0x3fffffff from memory map. So will the cs1 address range be 0x30000000-0x31000000? For example to access the first two bytes i can use: volatile uint8_t* byte1_ptr = (volatile uint8_t*)0x30000000 volatile uint8_t* byte2_ptr = (volatile uint8_t*)0x30000002 Is this correct? Looking forward to any reply, Regards Bernhard
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