hi,biser,
We also have no the datasheet on hand.And we only have the timing chart of the LCD.
The following chart is the STN timing of another CPU LCD controller.
the VFRAME is the VSYNC signal,and the VLINE is the HSYNC signal.The WDLY is what we want.How to add the delay time from the last hsync falling edge to the vsync rising edge?
we think the STN LCD maybe shifted the last line data to the first line of the next frame because the last hsync falling edge and the vsync rising edge are nearly generated at the same time in AM335X.