Hi Kumac,
This register sets the Data Macro 0 DQS Gate Slave Ratio (AM335X TRM Rev. J Table 7-256 and section 7.3.6.10). As mentioned in http://processors.wiki.ti.com/index.php/AM335x_DDR_PHY_register_configuration_for_DDR3_using_Software_Leveling and http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips#DDR_PHY_Registers there is no need to set this register, it can be left in its default state.