Tobias,
you might want to rephrase the question to work around the PRU issue :-). There are other bus masters in the device...
Anyway as the MMU is part of the ARM core block it is not visible at all to the other bus masters. So virtual addresses are not available for them I think. Otherwise all bus traffic would have to be routed through the ARM MMU. Not a good idea for system performance where we make heavy use of parallel bus transfers. In addition I don't know how that should work logically as MMU context typically changes with task context in HLOS. But how should the PRU know about that?
Regards.