Start by checking your clock tree..start at the master OSC and work downstream to the Ethernet portion ensuring that the frequency and dividers are correct. Check out Figure 6-11 in the TRM for a good overview of the clocking structure.
In your case, you are most concerned with CORE_CLOCKOUTM5 (250MHz) which is derived from Core PLL. Based on what you outlined above, I think this running at the wrong frequency...RGMII-1G @ 125MHz is derived directly from CORE_CLOCKOUTM5 with only a /2 divisor in the path...and you can't get 50MHz from 250MHz dividing by 2.
I'm betting you'll find CORE_CLOCKOUTM5 running at 100MHz instead of the required 250MHz.