Could you be more specific about the issue ?
I have been designing FPGA based interfaces which connect to PHy via RMMI.
And the data which comes out on RMII TX_EN/TXD0/TXD1 is mirrored on CRS_DV/RXD0/RXD1 ( at least in my implementation). So I cannot imagine what could be the issue once I skip management interface ( and use external 50MHz reference clock)
I my design I want to save cost taking away switch and would like to know to obstacle.
We do have FPGA and could route RMII signals through, but I would need to know what should be done to make sch connection running.