Is there any detailed information on how to configure and implement the pin mux settings for the AM33x using the Adeneo-based Compact 7 BSP? For several days I have been trying different combinations of configurations for the bsp_padcfg.h and bsp_padcfg.c without being able to flip a single output bit. I have successfully been able to control the GPIO3_4 bit which is already configured in the BSP, but enabling a non-standard pin like GPIO1_12, or GPIO1_21 seems to be more involved than just the following (in bsp_padcfg.h):
#define ANNUN_PADS \
PAD_ENTRY(GPMC_A5, MODE(7) | AM335X_PIN_OUTPUT) /* GPIO1_21 */ \
...and in bsp_padcfg.c:
const PAD_INFO AnnunPads[] = {ANNUN_PADS END_OF_PAD_ARRAY};
.
.
.
const EVM_PIN_MUX GP_BOARD_PIN_MUX[] = {
{ CTPPads, AM_DEVICE_CTP, PROFILE_0 | PROFILE_1 | PROFILE_2 | PROFILE_7, DEV_ON_DGHTR_BRD},
{ ADCTSCPads, AM_DEVICE_ADC_TSC, PROFILE_0 | PROFILE_1 | PROFILE_2 | PROFILE_7, DEV_ON_DGHTR_BRD},
{ BKLPads, AM_DEVICE_BKL, PROFILE_0 | PROFILE_1 | PROFILE_2 | PROFILE_7, DEV_ON_DGHTR_BRD},
//{ I2C0Pads, AM_DEVICE_I2C0, PROFILE_ALL, DEV_ON_BASEBOARD},
{ I2C1Pads, AM_DEVICE_I2C1, PROFILE_ALL, DEV_ON_BASEBOARD},
{ LCDCPads, AM_DEVICE_LCDC, PROFILE_0 | PROFILE_1 | PROFILE_2 | PROFILE_7, DEV_ON_DGHTR_BRD}, //although its separate LCD board, use BaseBoard as location; will use profile info to know if LCD is valid or not
{ MCASP0Pads, AM_DEVICE_MCASP0, PROFILE_ALL, DEV_ON_BASEBOARD},
//{ MCASP1Pads, AM_DEVICE_MCASP1, PROFILE_0 | PROFILE_3, DEV_ON_DGHTR_BRD},
{ MMC0Pads, AM_DEVICE_MMCHS0, PROFILE_ALL & ~PROFILE_5, DEV_ON_BASEBOARD},
//{ MMC0_NoCD_Pads, AM_DEVICE_MMCHS0, PROFILE_5, DEV_ON_BASEBOARD},
{ MMC1Pads, AM_DEVICE_MMCHS1, PROFILE_2, DEV_ON_DGHTR_BRD},
{ MMC2Pads, AM_DEVICE_MMCHS2, PROFILE_4, DEV_ON_DGHTR_BRD},
{ NANDPads, AM_DEVICE_NAND, PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3, DEV_ON_DGHTR_BRD},
{ NORPads, AM_DEVICE_NOR, PROFILE_3, DEV_ON_DGHTR_BRD},
//{ RGMIIMultiplePhyPads, AM_DEVICE_CPGMAC0, PROFILE_1 | PROFILE_2 | PROFILE_4 | PROFILE_6, DEV_ON_DGHTR_BRD},
//{ RGMIISinglePhyPads, AM_DEVICE_CPGMAC0, PROFILE_0 | PROFILE_3 | PROFILE_5 | PROFILE_7, DEV_ON_BASEBOARD},
{ VARPHYSPads, AM_DEVICE_CPGMAC0, PROFILE_ALL, DEV_ON_BASEBOARD},
{ SPI0Pads, AM_DEVICE_MCSPI0, PROFILE_2, DEV_ON_DGHTR_BRD},
{ SPI1Pads, AM_DEVICE_MCSPI1, PROFILE_3, DEV_ON_DGHTR_BRD},
{ UART0Pads, AM_DEVICE_UART0, PROFILE_ALL, DEV_ON_BASEBOARD},
{ UART1Pads, AM_DEVICE_UART1, PROFILE_ALL, DEV_ON_BASEBOARD},
{ UART2Pads, AM_DEVICE_UART2, PROFILE_ALL, DEV_ON_BASEBOARD},
{ UART3Pads, AM_DEVICE_UART3, PROFILE_ALL, DEV_ON_BASEBOARD},
{ USB0Pads, AM_DEVICE_USB0, PROFILE_ALL, DEV_ON_BASEBOARD},
{ AnnunPads, AM_DEVICE_GPIO1, PROFILE_ALL, DEV_ON_DGHTR_BRD},
{0},
};
Under the kernel debugger, I can't see any difference in the handling of the GPIOOpen(), GPIOSetMode(), and GPIOSetBit() handling between setting GPIO3_4 (which works), and setting GPIO1_21 (which doesn't). I feel there must be some other initialization that I am missing but have been unable to find any documentation.
