Hi Xiangtian,
You say that you are accessing NAND and NOR both at GPMC_CSn0. Is this a typo? You should know that this is not possible, they must be at different chip selects.
The three registers you mention are necessary only for NAND access, because NAND memories use a different interface over the GPMC - they receive commands, address and data over the GPMC data lines. For NOR access these registers are not used. You can access both NOR and NAND over the GPMC, but as mentioned above they must be at different chip selects. NOR memories are addressed over the GPMC address lines (or address/data lines if AD-mux mode is used) and data is exchanged over the GPMC data lines. NOR access is simply a read/write to a memory location.