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Forum Post: RE: AM335x with RMII Ethernet Phy

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The best explanation I've heard so far is that the hold from the AM3352 and the hold requirement at the TLK110 isn't a requirement to hold data valid, but is actually a timing requirement to the zero or threshold crossing.  This interpretation is consistent with the timing diagram in Figure 5-12 of SPRS717.pdf and Figure 9-23 of SLLS901D.  When I think of data valid, I think 2.0V and 0.8V, not threshold crossing. 

Perhaps this difference explains how the RMII TXD hold provided by the AM3352 and required by the TLK110 is acceptable.


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