hello,
i have a cache problem, i am now working with am3359 and sys/bios.
my arm use MCASP interface to send and receive data from fpga. i use edma with MCASP to send and receive data.
at first,i find my receive buffer has not updata, i find it is a cache coherence while use edma to receive data from mcasp. So i define a section in DDR3 as io,while means this section will not cache, and put my receive buffer in this section. but i find when when my fpga send data to my arm through mcasp，there always some error. i wonder if i define a section in ddr3 as io(no cache), is it very slow for me to access this data??
i also have another question, in am3359, i canot find the address of L1 and L2, there is only memory map of L3, i wonder if i can put my buffer in L1 or L2 and make the region no cache? i am use sys/bios,
thank you .