Steve and Brad,
Thanks for your answers that does clarify a lot. I have a few additional questions on this same topic but with respect to the SPI boot (specificly NOR flash hooked up via SPI):
It says in section 26.1.7.6.2 (Initialization / Functional Description / Memory Booting / SPI / Initializaion and Detection):
The ROM Code initializes the SPI controller, pin muxing and clocks for communicating with the SPI
device. The controller is initialized in Mode 3 and the clock is setup to operate at 12 MHz. There is no
specific device identification routine that is executed by the ROM code to identify whether a boot device is
preset or not. If no SPI device is present, the sector read will return only 0xFFFFFFFF and the SPI boot
will be treated as failed.
The highlighted statement appears to be pretty definitive and I would interpret it in such a way that the Boot ROM goes on and tries the next boot device in its list when something like that happens. But the next section in the TRM says “The ROM Code reads SPI data from the boot device in 512 byte sectors.”, which is then followed by table 26-29 that looks like this:
Memory | Max number of blocks checked | number of sectors searched |
NAND | first 4 | Number of sectors in one block |
SPI | first 4 | 1 |
So, this table says that the Boot ROM checks the first 4 _blocks_ in 1 sector. This is somewhat in conflict with the highlighted statement of the first paragraph and nowhere is stated what a ‘block’ is on a SPI device.
So the follow up SPI boot device questions are:
1) Are blocks and sectors equivalent?
2) Is it correct that the Boot ROM reads up to 4 consecutive 512 byte sectors?
3) How does the almost 1MB x-loader fit into a 512 byte sector? (section 26.1.9 says the GP header must be followed immediately by executable code, and that's bigger than 512 bytes)
4) What (if there is any) is the need for having multiple x-loaders in the SPI device if hooked up to NOR Flash?
Thanks
-Mike