Thanks, Biser. I have obtained the optimal parameters for our DDR3 with those tools and CCS provided by TI. But the reset problem still existed with these tuned parameters. After adding debug information, I solved this problem by adding a time delay in the beginning of the function board_init_f in arch/arm/lib/spl.c. The code shows that C environment is set in arch/arm/lib/crt0.S before calling board_init_f. I cannot figure out why such a delay is needed in our custom board, although everything seems OK now. Is it a hardware problem related to DDR? Could anyone given some opinions? Thanks.
Best regards,
Jason