Forum Post: SPI chip select high between word transmissions possible?

The SPI A/D chip I'm communicating with needs CS to go high for minimum 8 SCLK cycles between word transfers as part of its internal processing.  If I send one multiple-word transfers the CS line stays low.  If I send multiple single-word transfers, there's a very long delay between transfers that doesn't give me enough time to transfer all the data in the time required.  How would I force SPI chip select high between word transmissions?

I'm using spidev in linux to send the SPI messages.

Thanks for the help.

Alex