Hi Paul,
Thank you for your reply.
I am discussing how to use the Wait-In-Reset with CCS on other thread, but the topics except an emulator and CCS should be discussed here.
Can the AM335x be accessed via JTAG in the Wait-In-Reset configured by the EMU0/1 pins after Power On Reset?
[quote user="peaves"]
The AM335x EMU0 and EMU1 terminals must be high until this high logic state is latched on the rising edge of PWRONRSTn.
[/quote]
I saw the Errata. Advisory 1.0.36 describes that the EMU0/1 pins are sampled after the falling edge of WARMRSTn.
Are the EMU0/1 pins latched after the falling edge of WARMRSTn, not latched on the rising edge of PWRONRSTn?
Can any warm reset source be used to determine ICEPick boot mode?
Best regards,
Daisuke
