Your original post mentions Port 0 and Port 1. However, the external CPSW ports on AM335x are numbered 1 and 2 with port 0 being the internal port of CPSW.
I would like to confirm what type of Ethernet PHY is connected to each external port and which silicon revision of AM335x is being used.
It sounds like you have one port connected to an RGMII PHY and the other port connected to an RMII PHY. Which PHY is connected to external ports 1 and 2?
If you are using an RMII PHY on port 2, Usage Note 3.1.6 does not apply because the RMII2_CRS_DV signal function was added to the GPMC_A9 terminal. If you are using silicon revision 1.0 with an RMII PHY on port 2, Usage Note 3.1.4 may apply if you are trying to use the same terminal for GPMC_WAIT0 and RMII2_CRS_DV. If you are using any silicon revision with an MII PHY, the respective Usage Note (3.1.4 for silicon revision 1.0 and 3.1.6 for silicon revisions 2.x) applies if you are trying to use the same terminal for GPMC_WAIT0 and GMII2_CRS.
TRM section 1.2.6 is describing an enhancement implemented in silicon revision 2.x, where a new pin multiplexing option was added for the GPMC_A9 terminal. This is the difference between Usage Note 3.1.4 and Usage Note 3.1.6. The enhancement eliminates the pin multiplexing limitation related to RMII, but not MII.
If you are using an RMII PHY on port 2 there is an option to use the GPMC_A9 terminal for the RMII CRS_DV signal, so an external hardware solution will not be required. If you are using an MII PHY on port 2, an external hardware solution will be required.
Regards,
Paul