You don't control the switch during ROM code execution. You tie it for example to GPIO3_19 - this GPIO is low duing reset and remains low after reset is released (you can choose any free GPIO that's in the desired state during reset and after reset release - see Table 2-7 in the datasheet). Your sysboot pins are connected to AM335X at this time, and NOR address lines are pulled down. At some point ROM code jumps to execution of boot code from NOR flash. Somewhere during boot code execution pinmuxing is done for AM335X pins. As ROM code has configured only addresses up to A11 this pinmuxing has to happen inside the first 4kB of NOR flash code. You must ensure that your high addresses are pinmuxed as GPMC addresses. After that is done you set GPIO3_19 high and your AM335X high addresses are connected to the NOR flash. That's it, now you can address the entire NOR.
If you don't understand this explanation I'm sorry, I cannot explain it better.
